1. Field of the Invention
This invention relates to the field of electronics. More specifically the invention relates to a high speed ramp generator.
2. Background Art
In the prior art, ramp generators are generally closed loop integrator circuits. Because the ramp generator is an integrator with feedback, there is a time delay incident with the starting and stopping of the integrator. This time delay may not be desirable in some applications. One example of such an application is high speed data communication across an isolation barrier, as described herein.
An isolation barrier is generally used in applications in which it is desired to keep voltage potentials in one portion of a circuit isolated from voltages in another portion, e.g., to prevent relatively excessive and/or harmful voltages from entering a relatively low voltage or voltage sensitive circuit. Such applications may include, for example, telephony, medical, industrial, and other similar applications.
For example, in a telephony application, it may be necessary to protect communication circuitry from high voltages on the telephone line by placing an isolation barrier between the communication circuitry and the telephone line. However, while it is desirable to prevent harmful voltages from crossing from one side of an isolation barrier to the other, it is also desirable to facilitate signal communication between circuits on both sides of the barrier. In telephony applications, the isolation requirement is generally imposed by some governmental requirement (e.g., FCC part 68 in the US).
The transformer is one of several types of electrical devices that may be used as an element of an isolation barrier. However, in the prior art, digital communication across a transformer generally requires either a pulse transformer for each direction of communication, or time domain multiplexing of a pulse transformer (i.e., half-duplex communication). Prior art systems are incapable of full-duplex digital communication across a single transformer.
Half-duplex communication reduces communication bandwidth as each direction of communication must wait its turn to use the one-way signal channel. However, the use of multiple transformers to achieve two-way communication is expensive in terms of cost and space. A full duplex, single-transformer solution is therefore desired.
Unfortunately, the electrical characteristics of a transformer make it difficult to simultaneously drive a transmit signal onto, and detect a receive signal from, the same port of a transformer. For full-duplex signaling, it would be desirable and advantageous to have a system that can detect a receive signal across the same port of the transformer that is being used simultaneously to drive the transmit signal.
As described in the present inventor's US Patent Application 2004-0239487, entitled “Method and Apparatus for Full Duplex Signaling Across a Transformer” (incorporated herein by reference), the current into/out of the primary that is dependent upon the loading on the secondary can be separated out from the magnetizing current. By modulating the load impedance in the secondary, data can be sent from the secondary to the primary and detected from the load current on the primary side.
To separate out the load current at the primary, a corrective current signal from a ramp generator may be applied to the primary to cancel magnetizing current that the primary of the transformer might demand in such bi-directional communication across the barrier. However, the magnetizing current switches direction (i.e., ramping up or ramping down) in response to voltage transitions in the transmitted data signal (primary to secondary). Any delays in the performance of the ramp generator (e.g., onset or shut-off delays) can cause timing offsets in the corrective current signal, degrading the accurate cancellation of the magnetizing current and increasingly impacting receive data detection performance as the communication data rate rises.
As highlighted by the foregoing example, it would be desirable to have a ramp generator in which timing delays are minimized to improve performance in high-speed applications.